Logic Silicon
Logic Silicon seeks Physical Design Engineers for on‑site roles in Pakistan. 3‑5+ years ASIC design required. Apply: [email protected]
Logic Silicon is looking for experienced Physical Design Engineers to join its on‑site teams across Pakistan.
Responsibilities
- Execute the full ASIC Physical Design flow from RTL to GDSII.
- Perform floor planning, placement, clock tree synthesis, routing, and static timing analysis.
- Achieve timing closure while optimizing power, performance, and area (PPA).
- Address EM/IR issues and ensure design rule and LVS compliance.
- Use Cadence Innovus or Synopsys tools for implementation.
- Develop or modify TCL or Python scripts to automate tasks (optional).
Who Should Apply
- 3–5 years of hands‑on ASIC Physical Design experience (Senior level) or 5+ years for Expert/Lead roles.
- Proficiency with the RTL‑to‑GDSII flow and relevant EDA tools.
- Strong understanding of timing closure, PPA, EM/IR, DRC/LVS.
- Fresh graduates or candidates without professional ASIC Physical Design background should not apply.
How to Apply
Interested candidates should email their CV to [email protected].
To apply for this job please visit logicsilicon.com.
